In recent years, a battery holding time of a mobile phone terminal has been prolonged, and lower power consumption of a dynamic memory which requires refreshing for holding cell data and which is mounted on, such as a mobile phone terminal, is also demanded. As the dynamic memory mounted on a mobile phone terminal or the like, there are provided a DRAM (a dynamic random access memory) and a pseudo SRAM in which a memory core is formed of DRAM cells, and which is compliant with SRAM (static random access memory) interface specifications.
It is particularly important to reduce a consumption current (a standby current) of the dynamic memory at a time of standby in order to prolong a battery holding time in a waiting state that occupies a large portion of a usage state of the mobile phone terminal.
On the other hand, in the dynamic memory (DRAM or pseudo SRAM), selection of a word line (at a high level) is controlled by a boosted voltage higher than en external supply voltage in order to improve a margin for reading data which has been stored at a high level in a memory cell.
Further, in order to reduce sub-threshold leakage of a cell transistor, a level (a low level) of a word line when not selected is set to the level lower than a ground (GND) potential.
FIG. 8 is a diagram showing a typical example of a configuration of a word line driving circuit of the related art. Referring to FIG. 8, a word line driving circuit 10″ includes a PMOSFET 12 with a source thereof connected to a line (a sub-word decode line) RAI and an NMOSFET 18 with a source thereof connected to a power supply VKK. Gates of the PMOSFET 12 and the NMOSFET 18 are connected in common to a main word signal MWLB. Drains of the PMOSFET 12 and the NMOSFET 18 are connected in common to a word line (referred to as a “sub-word line” as well) WL. The word line driving circuit 10″ further includes an NMOSFET 20 with a source thereof connected to the power supply VKK, a drain thereof connected to the word line WL, and a gate thereof connected to a signal RAIB (that is a complementary signal of the line RAI). The main word signal MWLB is a complementary signal (an inverted signal obtained by inverting a signal on a main word line MWL) of the main word line MWL (not shown) disposed in common in a plurality of sub-arrays to be driven by the word line driving circuits (sub-word drivers), respectively. The main word signal MWLB is set to a low level when the main word line MWL is selected, and is set to a high level (to a boosted voltage) when the main word line MWL is not selected. A driving power supply for the word line driving circuit (a sub-word driver circuit) provided corresponding to each of the sub-arrays is supplied from a signal (a sub-word decode signal) RAI at a high level when the word line driving circuit is selected. The signal RAI is supplied from a RAI driver circuit now shown. A back gate of the PMOSFET 12 in FIG. 8 is connected to a boosted voltage VPP.
Referring to FIG. 8, when the word line WL is selected (during a word line selection period), the main word signal MWLB is set to a low level, the signal RAI is set to a high level, the signal RAIB is set to a low level, the PMOSFET 12 is turned on, the NMOSFET 18 is turned off, and the word line WL is driven and charged to a potential (a boosted potential) RAI. Since the signal RAIB is low at this point, the NMOSFET 20 is also turned off.
When the word line WL is not selected, the signal RAI is set to a low level, and the signal RAIB is set to a high level. At this point, the NMOSFET 20 is turned on, thereby discharging, to a potential VKK, the word line WL which has been charged to the potential RAI when the word line was selected. In case wherein when the signal RAI is set to a low level and the word line WL is not selected, the main word signal MWLB is high, the NMOSFET 18 is turned on and discharges the word line WL, together with the NMOSFET 20. In case the main word signal MWLB is low (such as when a word line driving circuit for other sub-array connected to the same main word line is activated), discharging of the world line WL by the NMOSFET 20 is performed.
When a word line is not selected in the word line driving circuit 10″ of the related art, a voltage difference between a gate of the transistor PMOSFET 12 and a drain of the transistor PMOSFET 12 becomes large. GIDL (Gate Induced Drain Leakage) will be therefore generated. In an example in FIG. 9 which will be described later, when a word line is not selected, the main word signal MWLB assumes 3.5V (that is a gate voltage of the PMOSFET 12), and the word line assumes −0.5V (that is a drain voltage of the PMOSFET 12). The voltage difference between the gate of the PMOSFET 12 and the drain of the PMOSFET 12 becomes 4.0V. The GIDL flows between a drain of a transistor and a substrate and between a source of the transistor and a substrate (as indicated by arrows (1) and (2)′ in FIG. 8), depending on a voltage difference between a gate of the transistor and the drain of the transistor and a voltage difference between the gate of the transistor and the source of the transistor. Accordingly, the larger the above-mentioned voltage difference is, the larger the GIDL becomes.
When the dynamic memory is in a standby state, a word line is in a non-selected state except that refreshing is performed for each several tens of micro seconds. Then, the GIDL is generated almost constantly.
When voltage set-up as shown in FIG. 9 is performed as an example, and when a scale of memory cells is set to 256 M bits (megabits), the GIDL becomes 80 μA (at a high temperature), which is no negligibly large.
In order to reduce the standby current, reduction of the GIDL becomes important.
Patent Document 1, for example, discloses a configuration in which switching control is performed in order to reduce the GIDL. In this configuration, two types of voltages constituted from a boosted voltage that has the same potential as that of a selection level (a high level) of a word line and a voltage lower than the selection level (high level) of the word line are generated in an internal circuit. When the word line is not selected during an active period where a read/write operation to a memory cell is performed, the switching control is performed so that a line of the boosted voltage is connected to a gate of a PMOSFET in a word line driving circuit. On the other hand, when the word line is not selected during a standby period where the read/write operation to the memory cell is not performed, the switching control is performed so that a line of the voltage lower than the boosted voltage is connected to the gate of the PMOSFET in the word line driving circuit. By changing an input level to the PMOSFET between an active time and a standby time when the word line is not selected, as described above, a gate-to-drain voltage difference of the PMOSFET is reduced at the standby time, thereby reducing the GIDL. Though the GIDL remains large at the active time, the GIDL is smaller than a current required for performing the read/write operation. Thus, the GIDL at the active time does not cause problem.
Referring to a memory circuit including a word line driving circuit and a logic circuit in Patent Document 2, at the active time, a source electrode line of MOS transistors (NMOSFETs) is maintained at a ground potential. At the standby time, the source electrode line is switched to a level higher than a ground voltage. A gate-to-drain voltage difference at the standby time is thereby reduced (because when the word line is not selected, the NMOSFETs are turned on at the word line driving circuit, and a potential at the source electrode line of each of the NMOSFETs becomes a potential at a drain of a corresponding PMOSFET). The GIDL is therefore reduced.
Patent Document 3 discloses a configuration including a PMOSFET (Q9) with a source thereof connected to a power supply VDDQ, an NMOSFET (Q8) with a source thereof connected to a power supply VSS, and a PMOSFET (Q11) and an NMOSFET (Q10) connected in parallel between drains of the PMOSFET (Q9) and the NMOSFET (Q8), as an input circuit (an input voltage tracking type bias voltage generation circuit) . Gates of the PMOSFET (Q11) and the NMOSFET (Q10) are connected to the power supplies VSS and VDDQ, respectively. Gates of the transistors PMOSFET (Q9) and NMOSFET (Q8) are connected to an input terminal VIN. Bias voltages are output to a differential amplifier circuit from drains of the PMOSFET (Q9) and NMOSFET (Q8), respectively. As described above, Patent Document 3 discloses the configuration in which the PMOSFETs are cascaded. However, Patent Document 3 discloses the input circuit, which is completely different from a driver of the present invention in terms of a problem and the configuration.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P-2005-158223A
[Patent Document 2]
JP Patent Kokai Publication No. JP-P-2005-192234A
[Patent Document 3]
JP Patent Kokai Publication No. JP-P-2000-306382A